1. Field
The present embodiments relate to a multiprocessor system and a method of operating the multiprocessor system.
2. Description of the Related Art
Generally, in a processor system, a method is employed in which a high-speed cache memory is installed between a processor and a main memory, i.e., a main memory unit, in order to balance the operating speeds between the processor and the main memory. Moreover, in a system requiring high processing capabilities, a multiprocessor system using a plurality of processors is used. In the multiprocessor system, for example, a cache memory installed in the multiprocessor system, in which a plurality of processors accesses data of a main memory via the cache memory, is provided corresponding to each of the processors. This cache memory is accessed from all the processors with a fixed access priority given for each processor (e.g., Japanese Unexamined Patent Application Publication No. H6-202949).
In a conventional multiprocessor system with a cache memory corresponding to each processor, each cache memory is accessed from all the processors, so that the efficiency of cache memory utilization is excellent. However, since the access priority (hierarchical level) to each cache memory is fixed, a delay time (latency) after the processor requests access to the cache memory until it receives data may be increased. For example, even when the hierarchical level for achieving the optimal latency differs for each application to be used, the hierarchical level of the cache memory is fixed. For this reason, the latency may increase depending on the application. Moreover, when the shared data accessed by a plurality of processors is present in any one of the cache memories, the transfer of the data to other cache memories might reduce the latency further. Even in this case, the data cannot be transferred between the cache memories, so that the latency will not be reduced.